3-verilog的使用-1

verilog的使用-1

1.判断上升沿

reg    s_d0;
reg    s_d1;
wire   signal_up ;
//判断信号的上升沿
assign  signal_up = (~touch_key_d1) & touch_key_d0;
always @ (posedge clk or negedge rst_n) beginif(rst_n == 1'b0) begins_d0<= 1'b0;s_d1<= 1'b0;endelse begins_d0<= signal_in;s_d1<= s_d0;end 
end

2.模块例化

uart_reveive #(                       //串口接收例化.CLK_FREQ       (CLK_FREQ),       //设置频率.UART_BPS       (UART_BPS))       //设置波特率
u_uart_receive(                 .sys_clk        (sys_clk), .sys_rst_n      (sys_rst_n),.uart_rxd       (uart_rxd),.uart_done      (uart_w_en),.uart_data      (uart_data_w));

3.时钟计数

reg [26:0] cnt;
always @(posedge clk or negedge rst_n) beginif (!rst_n)cnt<= 24'd0;else if (cnt< 24'd1000_0000)cnt<= counter + 1'b1;elsecnt<= 26'd0;
end

4.案件消抖

module key_debounce(input            sys_clk,          //外部50M时钟input            sys_rst_n,        //外部复位信号，低有效input            key_in,              //外部按键输入output reg       key_flag,         //按键数据有效信号output reg       key_value         //按键消抖后的数据  );reg [31:0] delay_cnt;
reg        key_reg;always @(posedge sys_clk or negedge rst_n) begin if (!rst_n) begin key_reg   <= 1'b1;delay_cnt <= 32'd0;endelse beginkey_reg <= key_in;				//非阻塞赋值，按键输入是wire类型的，随时可能有值的变化if(key_reg != key_in)          //一旦检测到按键状态发生变化(有按键被按下或释放)delay_cnt <= 32'd500_000;  //给延时计数器重新装载初始值（计数时间为10ms）else if(key_reg == key_in) begin  //在按键状态稳定时，计数器递减，开始10ms倒计时if(delay_cnt > 32'd0)delay_cnt <= delay_cnt - 1'b1;elsedelay_cnt <= delay_cnt;end           end   
end
always @(posedge sys_clk or negedge rst_n) begin if (!rst_n) begin key_flag  <= 1'b0;key_value <= 1'b1;          endelse beginif(delay_cnt == 32'd1) begin   //当计数器递减到1时，说明按键稳定状态维持了20mskey_flag  <= 1'b1;         //此时消抖过程结束，给出一个时钟周期的标志信号key_value <= key;          //并寄存此时按键的值endelse beginkey_flag  <= 1'b0;key_value <= key_value; end  end   
end

5.时钟分频模块

module clock_generator (input  clk_50m,       		// 50MHz输入时钟input  rst_n,         		// 异步低电平复位output reg clk_out,        	// 周期时钟输出
);
localparam CNT_CYCLE   = 50_000_000;   //1秒 = 50,000,000个周期
// 计数器定义
reg [26:0] cnt_add;     
// 1秒时钟生成
always @(posedge clk_50m or negedge rst_n) beginif (!rst_n) begincnt_add <= 0;clk_out <= 0;end else beginif (cnt_add == CNT_CYCLE>>1-1) begincnt_add <= 0;clk_out <= ~clk_out;  // 翻转产生50%占空比end else begincnt_add <= cnt_add + 1;endend
end