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cocotb value cocotb—基础语法对照篇

news 2025/8/20 21:16:33

cocotb—基础语法对照篇

在这里插入图片描述

import cocotb
from cocotb.triggers import Timer
from adder_model import adder_model
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
import random@cocotb.test()
async def adder_basic_test(dut):"""Test for 5 + 10"""cocotb.fork(Clock(dut.clk, 10, units='ns').start())A = 5B = 10#dut.A <= A#dut.B <= B  # 和下边两行等价dut.A.value =Adut.B.value =Bawait RisingEdge(dut.clk)await RisingEdge(dut.clk)assert dut.X.value == adder_model(A, B), "Adder result is incorrect: {} != 15".format(dut.X.value)@cocotb.test()
async def adder_randomised_test(dut):"""Test for adding 2 random numbers multiple times"""cocotb.fork(Clock(dut.clk, 5, units='ns').start())for i in range(10):A = random.randint(0, 15)B = random.randint(0, 15)#dut.A <= A#dut.B <= Bdut.A.value = Adut.B.value = Bawait RisingEdge(dut.clk)await RisingEdge(dut.clk)assert dut.X.value == adder_model(A, B), "Randomised test failed with: {A} + {B} = {X}".format(A=dut.A.value, B=dut.B.value, X=dut.X.value)

#adder_model.py
def adder_model(a: int, b: int) -> int:""" model of adder """return a + b

# Makefile
TOPLEVEL_LANG= verilog
PWD=$(shell pwd)VERILOG_SOURCES=./adder.vTOPLEVEL=adder
MODULE= test_adderSIM=icarusinclude $(shell cocotb-config --makefiles)/Makefile.sim

多文件tb，多文件dut

# makefile templateVERILOG_SOURCES = $(PWD)/submodule.sv $(PWD)/my_design.sv
# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file:
TOPLEVEL=my_design
# MODULE is the name of the Python test file:
MODULE=test_my_designinclude $(shell cocotb-config --makefiles)/Makefile.sim

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