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fpga助教面试题

news 2025/8/12 18:19:40

在这里插入图片描述
第一题

module sfp_pwm(
input wire clk, //clk is 200M
input wire rst_n,
input wire clk_10M_i,
input wire PPS_i,
output reg pwm
)
reg [6:0] cunt  ;always @(posedge clk ) beginif(!rst_n)cunt<=0;else if(cunt==19)   //200M是10M的20倍cunt<=0;elsecunt<=cunt+1;end
always @(posedge clk_10M_i ) beginif(!rst_n)pwm<=0;else if(PPS_i&&cunt<15)pwm<=1;else if(PPS_i==0&&cunt<10)pwm<=1;elsepwm<=0;end
endmodule

第二题需要用到vivado pll时钟这个ip核
因为1.023这个时钟无法直接产生可以先产生10.23M的时钟再通过分频产生1.023 M的时钟

`timescale 1ns / 1ps
module test_two(input  wire        clk, //clk is 60M input  wire        rst_n, output wire        clk_1023k_o, output wire        ca);
wire clk_out1;
wire resetn  ;
wire locked  ;
reg  [3:0]  cunt    ;
wire        clk_1023;
reg  [11:0] ca_r    ;assign resetn=(rst_n&&locked)?1:0;
assign clk_1023k_o=(cunt<5)?1:0; //1.023M时钟
assign ca=ca_r[0];
always @(posedge clk_out1 ) beginif(!resetn)cunt<=0;else if(cunt==9)cunt<=0;elsecunt<=cunt+1;    
end
always @(posedge clk_1023k_o ) beginif(!resetn)ca_r<=12'h124;elseca_r <= {ca_r[10:0], ca_r[11] ^ ca_r[10] ^ ca_r[7] ^ ca_r[5]};
endclk_wiz_0 instance_name(// Clock out ports.clk_out1(clk_out1),     // output clk_out1// Status and control signals.resetn(resetn), // input resetn.locked(locked),       // output locked// Clock in ports.clk_in1(clk));      // input clk_in1endmodule