Armv8/Armv9架构的学习大纲-学习方法-自学路线-付费学习路线
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ARM 64位架构介绍
- ARM 64位架构介绍
- ARM架构概况，v8-A及其他架构概况
- ARM架构扩展到v8-A, v8.1A, v8.2-A等版本
- v8-A介绍和原理
- 支持v7遗留代码
- AArch32和AArch64状态
- v7指令集变更
- 废弃
- 新增功能（一些新的64位特性也被添加到32位执行中）
64位平台架构概述
- 示例SoC
- 多核处理器
- 互连（ACE或CHI）
- 一致性和互连
- 分布式中断控制器
- 固件的角色
- 启动
A64指令集架构（ISA）
- 整数操作
- 指令集
- 整数操作
- 内存操作
- 堆栈
- 系统指令
- 系统控制寄存器
- 与v7支持和协处理器的关系
- 调用约定
- 内存访问（DRAM和设备）
- 排序模型
- 屏障
- dmb, dsb, isb
- 负载-获取和存储-释放
- 领域
- 信号量
- 屏障
- 缓存管理
- 排序模型
- 浮点，先进的SIMD，加密
- 寄存器和指令
- 异常级别
- 4个异常级别
- 栈模型，处理程序和线程
- 向量表
- 核心实现选择
- 切换AArch32和AArch64状态
- 异常和中断处理
- 控制异常和中断的传递
- 综合寄存器
- 切换异常级别
- 从异常中返回
- 分页
- 使用页表进行内存管理
- 4K, 16K和64K粒度
- 页大小
- 使用页表实现的特性，例如“永不执行”
- 地址空间技巧——不属于地址的一些字段，例如标签和指针认证
- TLB管理
EL2概述
- 处理器特性，适用于虚拟化
- 使用异常级别
- 内存管理
- 二级页表
- 内存分区
- I/O MMU (SMMU)
- 启动过程中使用EL2进行UEFI执行
- 增加了Secure EL2架构
缓存
- 硬件缓存一致性
- 软件责任
- 软件中的缓存控制
安全（TrustZone）
- TrustZone功能
- 安全内存
- 链接到其他架构中的TrustZone
- 32位或64位TrustZone
- 异常级别上的影响和Secure EL2的增加
- 切换TrustZone的位宽
- 动态TrustZone，也称为Realms，是ARM的机密计算架构的一部分
其他主题
- 核心电源管理，外部电源控制器
- 电源模式（休眠，关闭）
- WFI, WFE, SEV
- 调试（硬件和软件调试）
- 调试器，虚拟机监控程序，操作系统
- RAS（可靠性，可用性，可维护性）
- 启动过程
Introduction to ARM 64-bit Architecture
- Introduction to ARM 64-bit Architecture
- ARM architecture profiles, what is v8-A and the other architecture profiles
- ARM architecture extensions to v8-A, the v8.1A, v8.2-A, etc
- v8-A introduction and rationale
- Support for v7 legacy code
- AArch32 and AArch64 state
- v7 instruction set changes
- Deprecation
- Additional features (some new 64-bit features have also been added to 32-bit execution)
64-bit Platform Architecture Overview
- Sample SoC
- MP Core
- Interconnect (ACE or CHI)
- Coherency and the interconnect
- Distributed interrupt controller
- Role of firmware
- Booting
A64 ISA (Instruction Set Architecture)
- Integer operations
- Instruction set
- Integer operations
- Memory operations
- Stack
- System instructions
- System control registers
- Relationship to v7 support and co-processors
- Calling conventions
- Memory access (DRAM and device)
- Ordering model
- Barriers
- dmb, dsb, isb
- load-acquire and store-release
- Domains
- Semaphores
- Barriers
- Cache management
- Ordering model
- Floating point, advanced SIMD, crypto
- Registers and instructions
- Exception levels
- The 4 exception levels
- Stack model, handler and thread
- Vector table
- Core implementation choices
- Switching AArch32 and AArch64 state
- Exception and interrupt handling
- Control of delivery of exceptions and interrupts
- Syndrome registers
- Switching exception levels
- Return from exception
- Paging
- Memory management with page tables
- 4K, 16K and 64K granules
- Page sizes
- Features achieved with page tables, such as execute never
- Address space trickery – fields in pointers that are not part of the address, such as tags and pointer authentication
- TLB management
EL2 Overview
- Processor features intended for virtualization
- Use of exception levels
- Memory management
- Second level page tables
- Memory partitioning
- I/O MMU (SMMU)
- The use of EL2 for UEFI execution during boot
- Addition of Secure EL2 to the architecture
Caches
- Hardware cache coherency
- Software responsibilities
- Cache control in software
Security (TrustZone)
- TrustZone functionality
- Secure memory
- Links to TrustZone in other architectures
- 32-bit or 64-bit TrustZone
- Implications on exception levels, and the addition of secure EL2
- Switching bitness of TrustZone
- Dynamic TrustZone, also called Realms, part of ARM’s Confidential Compute Architecture
Other Topics
- Core power management, external power controller
- Power modes (dormant, shutdown)
- WFI, WFE, SEV
- Debug (hardware and software based debug)
- Debugger, hypervisor, OS
- RAS (Reliability, Availability, Serviceability)
- Boot process
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