[HDLBits] Exams/m2014 q4b
Implement the following circuit:
module top_module (input clk,input d, input ar, // asynchronous resetoutput q);always@(posedge clk or posedge ar) beginif(ar)q<=1'b0;elseq<=d;end
endmodule
Implement the following circuit:
module top_module (input clk,input d, input ar, // asynchronous resetoutput q);always@(posedge clk or posedge ar) beginif(ar)q<=1'b0;elseq<=d;end
endmodule